1. Field of the Invention
The present invention relates to differential amplification circuits for use in negative-feedback operational amplifiers.
The present application claims priority on Japanese Patent Application No. 2007-264532, the content of which is incorporated herein by reference.
2. Description of Related Art
Various types of differential amplification circuits and related circuitries have been developed and disclosed in various documents such as Patent Documents 1 to 5.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2005-340337
Patent Document 2: Japanese Unexamined Patent Application Publication No. H03-169107
Patent Document 3: Japanese Unexamined Patent Application Publication No. H05-014075
Patent Document 4: Japanese Unexamined Patent Application Publication No. S62-104305
Patent Document 5: Japanese Utility Model Application Publication No.
Different amplification circuits using current-mirror load circuits have been appropriately used for operational amplifiers because of high gains thereof. For example, Patent Document 1 is directed to a semiconductor integrated circuit device equipped with an internal voltage generation circuit which includes a voltage-follower circuit (i.e., a differential amplifier having a voltage-follower connection, see reference numeral 17 in FIG. 3), in which the input voltage is identical to the output voltage. In the present application, operational amplifiers are defined as differential amplification circuits having high amplification factors intensely subjected to feedback.
The present inventor has recognized the following problems, which will be described with reference to FIGS. 11 and 12.
FIG. 11 shows a typical constitution of a voltage-follower circuit using an operational amplifier, i.e., a differential amplifier DA1 having a pair of a noninverting input terminal “in(+)” and an inverting input terminal “in(−)” as well as an output terminal “out”. Herein, the inverting input terminal in(−) is connected to the output terminal out. The relationship between an input voltage Vin (applied to the noninverting input terminal in(+)) and an output voltage Vout in connection with the differential amplifier DA1 having a gain A is expressed as follows:Vout=A(Vin−Vout)Vout=(1−δ)Vin≅Vin
  δ  =      1          A      +      1      
In the above, if A=∞ so that δ=0, Vout=Vin, precisely. However, it is impossible to realize infinite gain; hence, an input offset voltage δVin should inevitably occur.
The occurrence of the input offset voltage will be described in detail with respect to a voltage-follower circuit shown in FIG. 12. In FIG. 12, the voltages of nodes OUTb and OUT are designated as V(OUTb) and V(OUT) respectively. If the voltage-follower circuit of FIG. 12 is placed in a ideal operation condition, the output voltage V(OUT) is identical to the input voltage V(IN), and the relationship of I1=I2=I0/2 is established among currents I1, I2, and I0 flowing through p-channel MOS (Metal Oxide Semiconductor) transistors M3 and M4 and an n-channel MOS transistor M0. In the ideal operation condition, not only the gate-source voltages of the transistors M3 and M4 but also the drain-source voltages of the transistors M3 and M4 should be equal to each other because of the relationship of I1=I2. Hence, V(OUT)=V(OUTb)=VDD−|VGS3|, where VDD designates a supply voltage, and VGS3 designates a gate-source voltage of the transistor M3. In other words, the ideal operation condition is the point that V(IN) is just equal to VDD−|VGS3|. If the input voltage V(IN) differs from VDD−|VGS3|, the output voltage V(OUT) follows up with the input voltage V(IN). This makes the drain voltage of the transistor M3 differ from the drain voltage of the transistor M4; hence, I1≠I2. The difference between I1 and I2 causes the gate-source voltage of a transistor M1 to differ from the gate-source voltage of a transistor M2. By use of a differential drain resistance rsd4 of the transistor M4, a current difference Al between the currents I1 and I2 is expressed as follows:
      Δ    ⁢                  ⁢    I    =                    I        2            -              I        1              =                            V          ⁡                      (            OUTb            )                          -                  V          ⁡                      (            OUT            )                                      rds        ⁢                                  ⁢        4            
Due to the current difference ΔI, the voltage difference should occur in a gate-source voltage VGS with respect to the transistors M1 and M2. By use of a mutual conductance gm2 of the transistor M2, a variation ΔVGS of the gate-source voltage VGS is expressed as follows:
      Δ    ⁢                  ⁢          V      GS        =            Δ      ⁢                          ⁢      I              gm      ⁢                          ⁢      2      
Therefore, an input offset voltage Voffset of the voltage-follower circuit of FIG. 12 is expressed by equation (1).
                                                        Voffset              =                            ⁢                                                V                  ⁡                                      (                    OUT                    )                                                  -                                  V                  ⁡                                      (                    IN                    )                                                                                                                          =                            ⁢                                                V                                      GS                    ⁢                                                                                  ⁢                    2                                                  -                                  V                                      GS                    ⁢                                                                                  ⁢                    1                                                                                                                          =                            ⁢                              Δ                ⁢                                                                  ⁢                                  V                                      GS                    ⁢                                                                                  ⁢                    2                                                                                                                          =                            ⁢                                                                    V                    ⁡                                          (                      OUTb                      )                                                        -                                      V                    ⁡                                          (                      OUT                      )                                                                                        rds                  ⁢                                                                          ⁢                                      4                    ·                    gm                                    ⁢                                                                          ⁢                  2                                                                                        (        1        )            
Equation (1) clearly shows the following points (1) and (2) in conjunction with a graph of FIG. 13 showing the relationship between V(IN), V(OUT), V(OUTb), and Voffset.    (1) In the condition in which V(OUTb) equals V(OUT), that is, when the drain voltage of the transistor M3 equals to the drain voltage of the transistor M4, the input offset voltage becomes zero.    (2) In other conditions, it is impossible to make the input offset voltage become zero because of the finite differential drain resistance rds4 of the transistor M4 which results in the finite gain rds4·gm2.
The above calculation neglects the differential drain resistances of the n-channel transistors M1 and M2; however, even when the calculation is modified in consideration of the differential drain resistances, the above conclusion is still sustained without change.
In order to reduce the input offset voltage, it is necessary to increase the differential drain resistance rds4 of the transistor M4 (forming a current-mirror load circuit) by increasing the gate length of the transistor M4. Due to a tradeoff between the gate length and the overall area of the transistor M4, when the gate length is adequately increased to neglect the input offset voltage, the overall chip area should be increased so as to push up the manufacturing cost.
It may be possible to form a cascode current mirror circuit in which an additional p-channel MOS transistor is connected in series to the drain of the transistor M4 applying the prescribed bias voltage to the gate thereof. However, the cascode current mirror circuit suffers from a problem in that the margin of operation voltage should be reduced by the drain voltage of the transistor newly connected in series.
In FIG. 12, VSS designates a ground voltage, and the n-channel MOS transistor functions as a constant current circuit for producing the current I0. A current mirror circuit (or a bias voltage generation circuit, not shown) is introduced to control the gate voltage of the transistor M0 such that the drain-source current thereof matches the current I0.